This invention relates to semiconductor devices and methods of manufacture, and more particularly to a technique for preventing pattern sensitivity in a dynamic RAM type of memory device.
Manufacture is well underway of MOS/LSI type dynamic memory devices having 64K bit density and a single 5 V supply as described in Electronics, Sept. 28, 1978, pp. 109-116. Single 5 V supply dynamic RAMs offer substantial advantages over the previous generations of three-supply dyanmic RAMS, such as the 4027 and 4116 devices, in the areas of reduced power dissipation, easier PC board layout, total TTL compatibility, etc. However, the -5 V substrate supply used in these prior 4K and 16K dynamic RAMs not only provided an adjusted internal threshold voltage for input TTL compatibility but also protected the internal nodes from ever being forward biased whenever significant current transients occur--it is not uncommon for dynamic RAMs to exhibit 50 to 100 MA transients. Huge transients in high performance devices almost preclude the use of on-chip substrate bias generators because these circuits can supply at best several hundred microamps. Consequently, devices as described in the abovementioned Electronics article use a grounded substrate so as not to compromise the speed of the part as would be necessary if an on-chip substrate bias were employed.
With all its advantages, grounded substrate bias has one disadvantage: unless adequate protection is made on all nodes, there is a possibility that minority carriers injected into the substrate will diffuse to the areas of the storage capacitors and discharge these nodes which store charge dynamically. This condition can cause failure upon testing the devices after manufacture; the test patterns are indeed much more stringent than occur in normal operation. Patterns of "1's" and 0's" are written in and read out to detect "pattern sensitivity." An extremely tough pattern that is normally used in testing by manufacturers and users of dynamic RAMs is called "refresh disturb," as will be later described.
It is the principal object of this invention to provide an improved semiconductor memory device and method of manufacture. Another object is to provide improved dynamic RAM devices which have single 5 V supply and no substrate bias, particularly such devices which do not exhibit pattern sensitivity upon testing.